1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly, to a method of fabricating an oxide-nitride-oxide ONO electrically erasable and programmable read only memory EEPROM device having two transistors for performing two bit operations, and a method of driving the ONO EEPROM device.
2. Description of Related Art
An ONO EEPROM device is one type of non-volatile semiconductor memory device and has an oxide-nitride-oxide (ONO) layer in the bottom of a gate. The nitride layer in the ONO EEPROM device is a dielectric layer trapping or de-trapping electrons for data programming, data erasing, and data readout in a memory cell.
Generally, the ONO EEPROM device applies a Fowler-Nordheim (F-N) tunneling phenomenon or channel hot electron injection (CHEI) to trap electrons. The F-N tunneling method consumes less current to trap electrons, but has longer trapping time. In contrast, the CHEI method has shorter trapping time, but consumes more current to trap electrons so that the number of electron-trapping cells is limited.
U.S. Pat. No. 5,768,192 discloses an ONO non-volatile memory device applying the CHEI method to trap electrons in the nitride layer. FIG. 1a illustrates a cross sectional configuration for a unit cell of a conventional ONO EEPROM device applying a CHEI method to write a data, that is, to program a data. FIG. 1b shows an equivalent circuit diagram for the unit cell of the conventional ONO EEPROM device.
Referring to FIG. 1a and FIG. 1b, the unit cell of the conventional ONO EEPROM device 10 comprises a cell transistor CT11 having a conductive gate 30 connected to a word line WL11 and source/drain junction areas 41 and 42 connected to a pair of bit lines BL11 and BL12, respectively.
The conventional ONO EEPROM device comprises a trapping dielectric layer 25 with the ONO structure stacking serially a bottom oxide layer 21, a nitride layer 22, and a top oxide layer 23 on a silicon substrate of a first conductive type, for example, on a channel area 43 of a p-type silicon substrate 20.
The conductive gate 30 connected to the word line WL11 is formed on the trapping dielectric layer 25. The source/drain junction areas 41 and 42 are formed on the silicon substrate 20, below both sides of the conductive gate 30, and are overlapped with the conductive gate 30.
The bottom oxide layer 21 of the trapping dielectric layer 25 is an electric isolation layer for the channel area 43 and the top oxide layer 23 is an electric isolation layer for the word line WL11. The nitride layer 22 between the bottom oxide layer 21 and the top oxide layer 23 is an electron-trapping layer for data retention.
The above described conventional EEPROM device applies pre-determined voltages to the conductive gate 30 and to a pair of bit lines, BL11 and BL12, connected to the source/drain junction areas 41 and 42, respectively. Therefore, the electrons in the channel layer are trapped on the nitride layer 22 so that data is written in a corresponding memory cell.
The conventional EEPROM device applies the CHEI method to program data to a memory cell. The CHEI method requires a considerable amount of current for writing data to numerous memory cells. Therefore, a confined amount of current also limits the number of memory cells for writing data.
In addition, excessive electron de-trapping in an electron-trapping layer generates disturbance phenomena for erasing data in a memory cell when the data in the memory cell of the conventional EEPROM device is erased, which results in lowering device reliability of the conventional EEPROM device.